A. Balasiński: search on Z-Library

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1

[IEEE Comput. Soc 4th IEEE International Workshop on System-on-Chip for Real-Time Applications - Banff, Alta., Canada (19-21 July 2004)] 4th IEEE International Workshop on System-on-Chip for Real-Time Applications - Design strategies for ESD protection in SOC

Iniewski, K., Axelrad, V., Shibkov, A., Balasinski, A., Syrzycki, M.

Year:

2004

Language:

english

File:

PDF, 282 KB

english, 2004

2

Optimization of sub-100-nm designs for mask cost reduction

Balasinski, Artur

Journal:

Journal of Micro/Nanolithography MEMS and MOEMS

Year:

2004

Language:

english

File:

PDF, 674 KB

english, 2004

3

Some properties of metal/insulator/semiconductor structures with BN and carbon thin layers formed by the reactive pulse plasma method on silicon or SiO2 substrates and annealing effects

J. Szmidt, A. Jakubowski, A. Balasiński

Journal:

Thin Solid Films

Year:

1986

Language:

english

File:

PDF, 520 KB

english, 1986

4

[IEEE Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - Banff, Alta., Canada (2005.07.20-2005.07.24)] Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - DfM for SoC (design-for-manufacturability for system on a chip)

Year:

2005

Language:

english

File:

PDF, 81 KB

english, 2005

5

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - 3.125 Gb/s Power Efficient Line Driver with 2-level Pre-emphasis and 2kV HBM ESD Protection

Iniewski, K., Axelrad, V., Shibkov, A., Balasinski, A., Magierowski, S., Dlugosz, R., Dabrowski, A.

Year:

2005

Language:

english

File:

PDF, 552 KB

english, 2005

6

A Simple Experimental Computer with Negative Basis

A. Łazarkiewicz and W. Balasiński

Journal:

Mathematics of Computation

Year:

1961

Language:

english

File:

PDF, 357 KB

english, 1961

7

Layout techniques and rules to reduce process-related variability

Balasinski, Artur

Journal:

Journal of Micro/Nanolithography MEMS and MOEMS

Year:

2007

Language:

english

File:

PDF, 685 KB

english, 2007

8

SPIE Proceedings [SPIE Microelectronics, MEMS, and Nanotechnology - Canberra, ACT, Australia (Wednesday 5 December 2007)] Microelectronics: Design, Technology, and Packaging III - Patterning techniques for next generation IC's

Balasinski, A., Hariz, Alex J., Varadan, Vijay K.

Year:

2007

Language:

english

File:

PDF, 364 KB

english, 2007

9

SPIE Proceedings [SPIE Microelectronics, MEMS, and Nanotechnology - Canberra, ACT, Australia (Wednesday 5 December 2007)] Microelectronics: Design, Technology, and Packaging III - New type of dummy layout pattern to control ILD etch rate

Pohland, Oliver, Hariz, Alex J., Varadan, Vijay K., Spieker, Julie, Huang, Chih-Ta, Govindaswamy, Srikanth, Balasinski, Artur

Year:

2007

Language:

english

File:

PDF, 346 KB

english, 2007

10

SPIE Proceedings [SPIE Photomask Technology 2005 - Monterey, California (Monday 3 October 2005)] 25th Annual BACUS Symposium on Photomask Technology - DfM requirements and ROI analysis for System-on-Chip

Balasinski, Artur, Weed, J. Tracy, Martin, Patrick M.

Year:

2005

Language:

english

File:

PDF, 146 KB

english, 2005

11

SPIE Proceedings [SPIE Advanced Lithography - San Jose, CA (Sunday 25 February 2007)] Design for Manufacturability through Design-Process Integration - Cost-performance tradeoff between design and manufacturing: DfM or MfD?

Balasinski, A., Wong, Alfred K. K., Singh, Vivek K., Cetin, J., Karklin, L.

Year:

2007

Language:

english

File:

PDF, 281 KB

english, 2007

12

SPIE Proceedings [SPIE Microelectronics, MEMS, and Nanotechnology - Canberra, ACT, Australia (Wednesday 5 December 2007)] Microelectronics: Design, Technology, and Packaging III - SoC variability evaluation and reduction

Balasinski, Artur P., Hariz, Alex J., Varadan, Vijay K., Smayling, Michael C., Axelrad, Valery

Year:

2007

Language:

english

File:

PDF, 465 KB

english, 2007

13

SPIE Proceedings [SPIE Photomask and Next Generation Lithography Mask Technology XII - Yokohama, Japan (Wednesday 13 April 2005)] Photomask and Next-Generation Lithography Mask Technology XII - Multi-layer masks: manufacturability considerations

Balasinski, Artur, Komuro, Masanori

Year:

2005

Language:

english

File:

PDF, 178 KB

english, 2005

14

SPIE Proceedings [SPIE Photomask Technology - Monterey, CA (Monday 8 September 2003)] 23rd Annual BACUS Symposium on Photomask Technology - Optimization of dummy pattern for mask data size reduction

Iandolo, Walter, Kimmel, Kurt R., Staud, Wolfgang, Gilboa, Yitzhak, Phan, Bill, Balasinski, Artur P.

Year:

2003

Language:

english

File:

PDF, 143 KB

english, 2003

15

Series resistance in a MOS capacitor with a thin gate oxide

K. Iniewski, A. Balasiński, B. Majkusiak, R.B. Beck, A. Jakubowski

Journal:

Solid-State Electronics

Year:

1989

Language:

english

File:

PDF, 380 KB

english, 1989

16

The influence of electron beam energy on defect density in MOS device quality oxides

A Balasiński, A Jakubowski, A Świt

Journal:

Year:

1988

Language:

english

File:

PDF, 268 KB

english, 1988

17

Interface properties in fluorinated (100) and (111)Si/SiO2 MOSFETs

A. Balasiński, M.H. Tsai, L. Vishnubhotla, T.P. Ma, H.H. Tseng, P.J. Tobin

Journal:

Microelectronic Engineering

Year:

1993

Language:

english

File:

PDF, 294 KB

english, 1993

18

On -radiation and electron beam dose and gate oxide thickness dependence of radiation defects in MOS capacitors

A. Balasiński, A. Jakubowski, T. Brożek, K. Iniewski

Journal:

physica status solidi (a)

Year:

1986

Language:

english

File:

PDF, 179 KB

english, 1986

19

Effects of combined x-ray Irradiation and hot-electron injection on NMOS transistors

Artur Balasinski, Wenliang Chen, Tso-Ping Ma

Journal:

Journal of Electronic Materials

Year:

1992

Language:

english

File:

PDF, 561 KB

english, 1992

20

Enhanced electron trapping near channel edges in NMOS transistors

Balasinski, A., Ma, T.-P.

Journal:

IEEE Transactions on Electron Devices

Year:

1992

Language:

english

File:

PDF, 729 KB

english, 1992

21

Lateral profiling of oxide charge and interface traps near MOSFET junctions

Chen, W., Balasinski, A., Ma, T.-P.

Journal:

IEEE Transactions on Electron Devices

Year:

1993

Language:

english

File:

PDF, 983 KB

english, 1993

22

[Japan Soc. Appl. Phys Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference - Tokyo, Japan (11-13 July 2000)] Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387) - A novel procedure to evaluate design scalability based on device performance linked to photolithography data

Karklin, L., Balasinski, A., Axelrad, V.

Year:

2000

Language:

english

File:

PDF, 204 KB

english, 2000

23

[IEEE 1997 55th Annual Device Research Conference Digest - Fort Collins, CO, USA (23-25 June 1997)] 1997 55th Annual Device Research Conference Digest - A novel transient current technique to characterize process-induced thin oxide damage

Balasinski, A., Singhal, P.M., Morgan, L., Hodges, N., Spinner, C.

Year:

1997

Language:

english

File:

PDF, 205 KB

english, 1997

24

[IEEE 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC) - Cambridge, MA, USA (2008.05.5-2008.05.7)] 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference - Yield Optimization with Model Based DFM

Balasinski, Artur, Pikus, Fedor, Bielawski, Jan

Year:

2008

Language:

english

File:

PDF, 205 KB

english, 2008

25

Impact of radiation-induced nonuniform damage near MOSFET junctions

Balasinski, A., Ma, T.-P.

Journal:

IEEE Transactions on Nuclear Science

Year:

1993

Language:

english

File:

PDF, 625 KB

english, 1993

26

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current in thin-film SOI/NMOSFET's

Binglong Zhang,, Balasinski, A., Ma, T.P.

Journal:

IEEE Electron Device Letters

Year:

1994

Language:

english

File:

PDF, 277 KB

english, 1994

27

[IEEE Comput. Soc IEEE 2000 1st International Symposium on Quality Electronic Design - San Jose, CA, USA (20-22 March 2000)] Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) - Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs

Axelrad, V., Cobb, N., O'Brien, M., Boksha, V., Do, T., Donnelly, T., Granik, Y., Sahouria, E., Balasinski, A.

Year:

2000

Language:

english

File:

PDF, 204 KB

english, 2000

28

Observation of two types of trapping centers in thin film transistors using charge pumping technique

Balasinski, A., Worley, J., Huang, K.W., Walters, J., Liou, F.T.

Journal:

IEEE Electron Device Letters

Year:

1995

Language:

english

File:

PDF, 257 KB

english, 1995

29

[IEEE 1991 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (22-24 May 1991)] 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers - Lateral distribution of hot-carrier-induced oxide charge and interface traps in MOSFET's

Chen, W., Balasinski, A., Ma, T.-P.

Year:

1991

Language:

english

File:

PDF, 309 KB

english, 1991

30

Multilayer and Multiproduct Masks: Cost Reduction Methodology

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2006

Language:

english

File:

PDF, 650 KB

english, 2006

31

Ionizing radiation damage near CMOS transistor channel edges

Balasinski, A., Ma, T.P.

Journal:

IEEE Transactions on Nuclear Science

Year:

1992

Language:

english

File:

PDF, 514 KB

english, 1992

32

[American Vacuum Soc 1998 3rd International Symposium on Plasma Process-Induced Damage - Honolulu, HI, USA (4-5 June 1998)] 1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100) - Characterization of plasma induced damage using transient current measurements

Balasinski, A., Petti, C., Bamnolker, H., Ramkumar, K., Chung, A.

Year:

1998

Language:

english

File:

PDF, 418 KB

english, 1998

33

[IEEE 1993 International Symposium on VLSI Technology, Systems, and Applications Technical Papers - Taipei, Taiwan (12-14 May 1993)] 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers - Fluorinated CMOSFETs fabricated on (100) and (111) Si substrates

Balasinski, A., Vishnubhotla, L., Ma, T.P., Tseng, H.-H., Tobin, P.J.

Year:

1993

Language:

english

File:

PDF, 320 KB

english, 1993

34

Effects of X-ray irradiation on GIDL in MOSFETs

Acovic, A., Hsu, C.C.-H., Hsia, L.-C., Balasinski, A., Ma, T.-P.

Journal:

IEEE Electron Device Letters

Year:

1992

Language:

english

File:

PDF, 300 KB

english, 1992

35

[IEEE 2006 6th International Workshop on System on Chip for Real Time Applications - Cairo, Egypt (2006.12.27-2006.12.29)] 2006 6th International Workshop on System on Chip for Real Time Applications - Intelligent Fill Pattern and Extraction Methodology for SoC

Balasinski, Artur, Cetin, Joseph

Year:

2006

Language:

english

File:

PDF, 1.59 MB

english, 2006

36

A charge pumping method for rapid determination of interface-trap parameters in metal-oxide-semiconductor devices

Chen, Wenliang, Balasinski, Artur, Ma, T.-P.

Journal:

Review of Scientific Instruments

Year:

1992

Language:

english

File:

PDF, 627 KB

english, 1992

37

[IEEE International Electron Devices Meeting - Washington, DC, USA (10-13 Dec. 1995)] Proceedings of International Electron Devices Meeting - Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping

Balasinski, A., Worley, J., Zamanian, M., Liou, F.T.

Year:

1995

Language:

english

File:

PDF, 365 KB

english, 1995

38

[IEEE 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - Boston, MA, USA (12-14 Sept. 2000)] 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072) - Optimizing the cost of design rule modifications for subsequent generations of semiconductor technology

Year:

2000

Language:

english

File:

PDF, 561 KB

english, 2000

39

[IEEE 2006 6th International Workshop on System on Chip for Real Time Applications - Cairo, Egypt (2006.12.27-2006.12.29)] 2006 6th International Workshop on System on Chip for Real Time Applications - SoC Design Quality, Cycletime, and Yield Improvement Through DfM

Cetin, Joseph, Balasinski, Artur

Year:

2006

Language:

english

File:

PDF, 1.97 MB

english, 2006

40

Hot-carrier effects on interface-trap capture cross sections in MOSFETs as studied by charge pumping

Chen, W., Balasinski, A., Zhang, B., Ma, T.-P.

Journal:

IEEE Electron Device Letters

Year:

1992

Language:

english

File:

PDF, 219 KB

english, 1992

41

Evolution of capture cross-section of radiation-induced interface traps in MOSFETs as studied by a rapid charge pumping technique

Chen, W., Balasinski, A., Ma, T.-P.

Journal:

IEEE Transactions on Nuclear Science

Year:

1992

Language:

english

File:

PDF, 498 KB

english, 1992

42

[IEEE 2006 6th International Workshop on System on Chip for Real Time Applications - Cairo, Egypt (2006.12.27-2006.12.29)] 2006 6th International Workshop on System on Chip for Real Time Applications - A Method to Evaluate Power Domain Problems in SoC

Cetin, Joseph, Balasinski, Artur

Year:

2006

Language:

english

File:

PDF, 782 KB

english, 2006

43

[IEEE 1995 International Symposium on VLSI Technology, Systems, and Applications. - Taipei, Taiwan (31 May-2 June 1995)] 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers - Mobility and reliability improvements of fluorinated gate oxide for VLSI technology

Vishnubhotla, I., Balasinski, A., Wang, X.W., Ma, T.P., Tseng, H.H., Tobin, P.J.

Year:

1995

Language:

english

File:

PDF, 293 KB

english, 1995

44

Lateral distribution of radiation-induced damage in MOSFETs

Chen, W., Balasinski, A., Ma, T.-P.

Journal:

IEEE Transactions on Nuclear Science

Year:

1991

Language:

english

File:

PDF, 511 KB

english, 1991

45

[IEEE International Electron Devices Meeting 1999. Technical Digest - Washington, DC, USA (5-8 Dec. 1999)] International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) - A novel approach to simulate the effect of optical proximity on MOSFET parametric yield

Balasinski, A., Gangala, H., Axelrad, V., Boksha, V.

Year:

1999

Language:

english

File:

PDF, 391 KB

english, 1999

46

[IEEE 7th International Symposium on Quality Electronic Design (ISQED'06) - San Jose, CA, USA (27-29 March 2006)] 7th International Symposium on Quality Electronic Design (ISQED'06) - Question: DRC or DfM ? Answer: FMEA and ROI

Year:

2006

Language:

english

File:

PDF, 238 KB

english, 2006

47

Identification of Si∕SiO[sub 2] Interface Properties in Thin Film Transistors with Charge Pumping Technique

Journal:

Journal of The Electrochemical Society

Year:

1995

Language:

english

File:

PDF, 576 KB

english, 1995

48

Design for Manufacturability || DfM at 28 nm and Beyond

Balasinski, Artur

Year:

2014

Language:

english

File:

PDF, 5.44 MB

english, 2014

49

A Novel Procedure for Evaluating Design Scalability Based on Device Performance Linked to Photolithography

Karklin, Linard, Balasinski, Artur, Axelrad, Valery

Journal:

Japanese Journal of Applied Physics

Year:

2000

Language:

english

File:

PDF, 160 KB

english, 2000

50

[IEEE 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings - Boston, MA, USA (8-10 Sept. 1999)] 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) - Comparison of mask writing tools and mask simulations for 0.16 μm devices

Balasinski, A., Coburn, D.

Year:

1999

Language:

english

File:

PDF, 484 KB

english, 1999